Hardware description languages (HDLs) have long been used in the simulation and synthesis of electronic circuits. One particular HDL, known as Verilog, is widely used and is recognized as IEEE Standard 1364.
In the Verilog HDL, modules developed using the C programming language are conventionally used to model the behavior of functions and algorithms. Conventional co-simulation techniques use a programming language interface (PLI) to serve as an interface between the Verilog HDL and C models. The PLI includes an interface, a set of routines to interact with the Verilog simulation environment, and a set of routines to access Verilog internal data structures. Accordingly, the PLI enables user-supplied C code to interact dynamically with the Verilog simulation and internal data structures.
Recently, C++ based behavior modeling languages have emerged. Among such languages, SystemC from Synopsis, Inc. is one of the most popular among designers. Compared to the standard C++ programming language, the SystemC programming language provides additional functionality for timing, scheduling, and logic vectors, which are crucial in modeling certain behaviors of hardware. Because of these features, C++ based modeling languages, and SystemC in particular, are quickly gaining ground in the world of hardware logic design and simulation.
Despite these advantages, a problem has been introduced when using SystemC for co-simulation with the Verilog/PLI modules. SystemC modules are no longer procedural functions, but rather stand-alone objects. There is no intuitive way to pass the parameters from Verilog/PLI modules to SystemC modules in a function calling manner.
Verilog/PLI is currently used to co-simulate Verilog and C modules. In Verilog/PLI, however, the PLI calls the C function directly, and Verilog and C run in a single process space. Because SystemC modules are not procedural functions, they cannot be called in the same manner as C modules. Thus, conventional techniques for co-simulating Verilog and C modules are ineffective for co-simulating Verilog and SystemC modules. Accordingly, a need continues to exist for a technique for facilitating Verilog/PLI and SystemC co-simulation.